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pre - production t his is a product in the pre - production ph ase of development. device ramtron international corporation characterization is complete and ramtro n does not expect to change the 1850 ramtron drive, colorado springs, co 80921 specifications . ramtron will issue a product change notice if any (800) 545 - fram, (719) 481 - 7000 specification changes are made . http://www.ramtron.com rev. 2.1 june 2011 page 1 of 14 fm 28v020 256k bit bytewide f - ram memory features 256k bit ferroelectric nonvolatile ram ? organized as 32k x 8 ? 10 14 read/write cycles ? nodelay? writes ? page mode operation ? advanced high - reliability ferroelectric process superior to battery - backed sram mod ules ? no battery concerns ? monolithic reliability ? true surface mount solution, no rework steps ? superior for moisture, shock, and vibration ? resistant to negative voltage undershoots sram replacement ? jedec 32k x8 sram pinout ? 70 ns access time , 140 ns cycle time low power operation ? 2.0 v C 3.6v power supply ? standby current 9 0 ? a (typ) ? active current 7 ma (typ) industry standard configurations ? industrial temperature - 40 ? c to + 85 ? c ? 28 - pin g reen /rohs soic ( - s g) ? 32 - pin green/rohs tsop ( - tg) general description the fm 28v020 is a 32k x 8 nonvolatile memory that reads and w rites like a standard sram . a ferroelectric random access memory or f - ram is nonvolatile , which means that data is retained after power is removed . it provides data retention for over 10 years while eliminating the reliability concerns, functional disadvan tages , and system design complexities of battery - backed sram (bbsram). fast write timing and virtually unlimited write endurance make f - ram superio r to other types of memory. in - system operation of the fm 28v020 is very similar to other ram devices and ca n be used as a drop - in replacement for standard sram . read and write cycles may be triggered by /ce or simply by changing the address. the f - ram memory is nonvolatile due to its unique ferroelectric me mory process. these feature s make the fm 28v020 ideal fo r nonvolatile memory applications requiring frequent or rapid writes in the form of an sram. device specifications are guaranteed over the industrial temperature range - 40 c to + 85 c. pin configuration ordering information fm 28v020 - s g 28 - pin green /rohs soic FM28V020 - sgtr 28 - pin green/rohs soic, tape & reel FM28V020 - tg 32 - pin green/rohs tsop FM28V020 - tgtr 32 - pin green/rohs tsop, tape & reel tsop - i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc oe a11 a9 a8 a13 we vdd a14 a12 a7 a6 a5 a4 a3 nc 32 31 3 0 29 28 27 26 25 24 23 22 21 20 1 9 1 8 17 nc a 10 ce dq7 dq6 dq5 dq4 dq3 vss dq2 dq1 dq0 a0 a1 a2 n c s o i c 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 a 1 4 a 3 a 2 a 1 a 0 d q 0 d q 1 d q 2 v s s d q 4 d q 5 d q 6 d q 7 o e a 8 a 1 3 w e a 9 a 1 0 a 1 1 v d d a 1 2 a 7 a 6 a 5 a 4 c e d q 3
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 2 of 14 figure 1. block diagram pin description s pin name type pin description a(1 4 :0) input address inputs: the 15 address lines select one of 32,768 bytes in the f - ram array. the address value is latched on the falling edge of /ce . addresses a(2:0) are used for page m ode read and write operations. /ce input chip enable input : the device is selected and a new memory access begins on the falling edge of /ce. the entire address is latched internally at this point. /we input write enable: a write cycle begins when /we is asserted. t he rising edge causes t he fm 28v020 to write the data on the dq bus to the f - ram array. the falling edge of /we latches a new column address for fast page mode write cycles. /oe input output enable: when /oe is low, the fm 28v020 drives the da ta bus when valid data is available. deasserting /oe high tri - states the dq pins. dq(7:0) i/o data: 8 - bit bi - directional data bus for accessing the f - ram array. vdd supply supply voltage vss supply ground cont rol logic we a(14:3) a(2:0) i/o latch & bus driver oe dq(7:0) 4k x 64 f - ram array a(14:0) column de coder . . . address latch row decoder ce
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 3 of 14 functional truth table /ce /we a(14:3) a(2:0) operation h x x x standby/idle ? h v v read l h no change change page mode read l h change v random read ? l v v /ce - controlled write 2 l ? v v /we - controlled write 2, 3 l ? ? no change v page mode write 4 ? x x x starts precharge notes: 1) h=logic high, l=logic low, v=valid address, x=dont care. 2) for write cycles, data - in is latched on the rising edge of /ce or /we, whichever comes first. 3) /we - controlled write cycle begins as a read cycle and a( 14 :3) is latched then. 4) addresses a(2:0) must remain stable for at least 15 ns during page m ode operation.
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 4 of 14 overview the fm 28v020 is a bytewide f - ram memory logically organized as 32,768 x 8 and is accessed using an industry standard parallel interface. all data written to the part is immediately nonvolatile with no delay. the device offers pag e mode operation which provides higher speed access to addresses within a page (row). an access to a different page is triggered by toggling the chip enable pin or simply by changing the upper address a(14:3). memory operation users acces s 32,768 memory l ocations with 8 data bits each through a parallel interface. the f - ram array is organi zed as 8 blocks each having 512 rows. each row has 8 column locations, which allows fast access in page mode operation. once an initial address has been latched by the fa lling edge of /ce, subsequent column locations may be acces sed without the need to toggle the chip enable . when either chip enable pin is deasserted, a precharge operation begins . writes occur immediately at the end of the access with no delay. the /we p in must be toggled for each write operation. read operation a read operation begi ns on the falling edge of /ce. t he /ce - initiated access causes the address to be latched and starts a memory read cycle if /we is high. data becomes available on the bus afte r the acces s time has been satisfied. once the address has been latched and the access completed , a new access to a random location (different row) may begin while /ce is still active . the minimum cycle time for random addresses is t rc . note that unlike s rams, the fm 28v020 s /ce - initiated access time is faster than the address cycle time . the fm 28v020 will drive the data bus only when /oe is asserted low and the memory access time has been satisfied. if /oe is asserted prior to completion of the memory ac cess, the data bus will not be driven until valid data is available. this feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. when /oe is inactive , the data bus will remain hi - z . write operation writes occur in the fm 28v020 in the same time interval as reads. the fm 28v020 supports both /ce - and /we - controlled w rite cycles. in both cases, the address is latched on the falling edge of /ce. in a ce - controlled write, the /we signal is asse rted prior to beginning the memory cycle. th at is, /we is low when the device is activated with the chip enable . in this case, the device begins the memory cycle as a write. the fm 28v020 will not drive the data bus regardless of the state of /oe as long as /we is low. input data must be valid when the device is deselected with the chip enable . in a /we - controlled write, the memory cycle b egins when the device is activated with the chip enable . the /we signal falls some time later . therefore, the memory cyc le begins as a read. the data bus will be driven if /oe is low, however it will hi - z once /we is asserted low . the /ce - and /we - controlled write timing cases are shown on page 9 . in the write cycle timing 2 diagram, t he data bus is shown as a hi - z conditi on while the chip is write - enabled and before the required setup time. although this is drawn to look like a mid - level voltage, it is recommended that all dq pins comply with the minimum v ih /v il operating levels. write access to the array begins on the f alling edge of /we after the memory cycle is initiated. the write access terminates on the deassertion of /we or /ce, whichever come s first. a valid write operation requires the user to meet the access time specification prior to deasserting /we or /ce . da ta setup time indicates the interval during which data cannot change prior to the end of the write access . unlike other truly nonvolatile memory technologies, there is no write delay with f - ram . since the read and write access times of the underlying mem ory are the same, the user experiences no delay through the bus. the entire memory operation occurs in a single bus cycle. data polling, a technique used with eeproms to determine if a write is complete, is unnecessary. page mode operation the fm 28v020 pr ovides the user fast access to any data within a row element. each row has eight column locations. an access can start anywhere within a row and other column locations may be accessed without the need to toggle the /ce pin. for page mode reads, once the first data byte is driven onto the bus, the column address inputs a(2:0) may be changed to a new value. a new data byte is then driven to the dq pins. for page mode writes, the first write pulse defines the first write access. while the device is sele ct ed (/ce low ), a subsequent write pulse along with a new column address provides a page mode write access. precharge operation the precharge operation is an internal condition in which the state of the memory is preparing for a new access. precharge is user - initiated by driving at least one of the chip enable signal s to an inactive state . the
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 5 of 14 chip enable must remain inactive for at least the minimum precharge time t pc . precharge is also activated by changing the upper addess a(14:3). the current row is fi rst c losed prior to accessing the new row . the device automatically detects an upper order address change which s tarts a precharge operation, the new address is latched , and the new read data is valid within the t aa address access time. refer to the read cycle timing 1 diagram on page 9 . likewise a similar sequence occurs for wr i te cycles. refer to the write cycle timing 3 diagram on page 11 . the rate at which random addresses can be issued is t rc and t wc , respectively. endurance the FM28V020 is ca pable of being accessed at least 10 14 times C reads or writes. an f - ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis. the f - ram architecture is based on an array of rows and columns. rows are de fined by a14 - a3 and column addresses by a2 - a0. the array is organized as 4k rows of 8 - bytes each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endu rance calculation if the addressing is contiguous in nature . the user may choose to store cpu instructions and run them from a certain address space. the table below shows endurance calculations for 256 - byte repeating loop, which includes a starting addr ess and initial access , 7 page mode accesses, and a ce precharge. the number of bus clocks needed to complete an 8 - byte read transaction is 1+7 +1 or 9 clocks. the entire loop causes each byte to experience only one endurance cycle. f - ram read and write en du rance is virtually unlimited . table 1. time to reach 100 trillion cycles for repeating 256 - byte loop bus freq (mhz) bus cycle time (ns) 256 - byte transaction time ( ? 14 cycles 10 100 28.8 34,720 1.09 x 10 1 2 91.7 5 200 57.6 17,360 5.47 x 10 1 1 182.8
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 6 of 14 sram drop - in replacement the fm 28v020 has been designed to be a drop - in replacement for standard asynch ronous srams. the device does not require /ce to toggle for each new address. /ce may remain low indefinitely while v dd is applied. when /ce is low, the device automatically detects address c hanges and a new access begins . it also allows page mode operat ion at speeds up to 15 mhz. a typical application is shown in figure 2. it shows a pullup resistor on /ce which will keep the pin high during power cycles assuming the mcu/mpu pin tri - states during the reset condition. the pullup resistor value should be chosen to ensure the /ce pin tracks v dd yet a high enough value that the current drawn when /ce is low is not an issue. figure 2 . typical application using pullup resistor on /ce for applications that require the lowest pow er consumption, the /ce signal should be active only during mem ory accesses. due to the external pullup resistor, some supp ly current will be drawn while /ce is low . when /ce is high, the device draws no more than the maximum standby current i sb . note t hat if /ce is ground ed , the user must be sure /we is not low at powerup or powerdown events. if the chip is enabled and /we is low during power cycles, data corruption will occur. figure 3 shows a pullup resistor on /we which will keep the pin high during power cycles assuming the mcu/mpu pin tri - states during the reset condition. the pullup resistor value should be chosen to ensure the /we pin tracks v dd yet a high enough value that the current drawn when /we is low is not an issue. a 10kohm resistor dra ws 330ua when /we is low and v dd =3.3v. figure 3 . use of pullup resistor on /we the fm 28v020 is backward compatible with the 256kbit fm18l08 device . o perating the fm 28v020 with /ce toggling low on every address is perfectly a cceptable. pcb layout recommendations a 0.1uf decoupling capacitor should be placed close to pin 28 (v dd ) and the ground side of the capacitor should be connected to either a ground plane or low impedance path back to pin 1 4 (v ss ). it is best to use a ch ip capacitor that has low esr and has good high frequency characteristics. if the controller drives the address and chip enable from the same timing edge, it is best to keep the address routes short and of equal length. a simple rc circuit may be inserte d in the chip enable path to provide some delay and timing margin for the fm28v 0 2 0s address setup time t as . as a general rule, the layout designer may need to add series termination resistors to controller outputs that have fast transitions or routes tha t are > 15cm in length. this is only necessary if the edge rate is less than or equal to the round trip trace delay. signal overshoot and ringback may be large enough to cause erratic device behavior. it is best to add a 50 ohm resistor (30 C 60 ohms) ne ar the output driver (controller) to reduce such transmission line effects. ce we oe a(14:0) dq(7:0) FM28V020 v dd mcu/ mpu r ce we oe a(14:0) dq(7:0) FM28V020 v dd mcu/ mpu r
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 7 of 14 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to + 4.5 v v in voltage on any signal pin with r espect to v ss - 1.0v to + 4.5 v and v in < v dd +1v t stg storage temperature - 55 ? c to +125 ? c t lead lead temperature (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q1 00 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 2kv 1.25kv 200v package moisture sensitivity level msl - 2 (soic) msl - 3 (tsop) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational secti on of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect dev ice reliability. dc operating conditions ( t a = - 40 ? c to + 85 ? c, v dd = 2.0 v to 3.6v unless otherwise specified) symbol parameter min typ max units notes v dd power supply 2.0 3.3 3.6 v i dd v dd supply current 7 12 ma 1 i sb standby current C ? li input leakage current ? ? lo output leakage current ? ? ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage - 0.3 0.3 v dd v v oh1 output high voltage ( i oh = - 1 ma, v dd =2.7v) 2.4 v v oh2 output high voltage ( i oh = - 100 ? a) v dd - 0.2 v v ol1 output low voltage ( i ol = 1 ma , v dd =2.7v) 0.4 v v ol2 output low voltage ( i ol = 150 ? a) 0.2 v notes 1. v dd = 3.6v, /ce cycling at minimum cycle time. all inputs at cmos levels (0.2v or v dd - 0.2v) , all dq pins unloaded. 2. v dd = 3.6v, /ce at v dd , all other pins at cmos levels (0.2v or v dd - 0.2v) . 3. v in , v out between v dd and v ss .
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 8 of 14 read cycle ac parameters (t a = - 40 ? c to + 85 ? c, c l = 30 pf, v dd = 2.0v to 3.6v unless otherwise specified) symbol parameter min max units notes t rc read cycle time 140 - ns t ce chip enable access time - 70 ns t aa address access time - 140 ns t oh output hold time 20 - ns t aap page mode address access time - 6 0 ns t ohp page mode output hold time 3 - ns t ca chip enable active time 70 - ns t pc precharge time 70 - ns t as address setup time (to /ce low) 0 - ns t ah address hold time (/ce - controlled) 70 - ns t oe output enable access time - 15 ns t hz chip enable to output high - z - 10 ns 1 t ohz output enable high to output high - z - 10 ns 1 write cycle ac parameters (t a = - 40 ? c to + 85 ? c , v dd = 2.0v to 3.6v unless otherwise specified) symbol parameter min max units notes t wc write cycle time 140 - ns t ca chip enable active time 70 - ns t cw chip enable to write enable high 70 - ns t pc precharge time 70 - ns t pwc page mode write enable cycle time 3 0 - ns t wp write enable pulse width 18 - ns t as address setup time (to /ce low) 0 - ns t ah address hold time (/ce - controlled) 70 - ns t asp page mode address setup time (to /we lo w) 5 - ns t ahp page mode address hold time (to /we low) 15 - ns t wlc write enable low to /ce high 25 - ns t wla write enable low to a(14:3) change 25 - ns t awh a(14:3) change to write enable high 140 - ns t ds data input setup time 15 - ns t dh da ta input hold time 0 - ns t wz write enable low to output high z - 10 ns 1 t wx write enable high to output driven 5 - ns 1 t ws write enable to /ce low setup time 0 - ns 1,2 t wh write enable to /ce high hold time 0 - ns 1,2 notes 1 this parameter is char acterized but not 100% tested. 2 the relationship between /ce and /we determines if a /ce - or /we - controlled write occurs. power cycle timing (t a = - 40 ? c to + 85 ? c, v dd = 2.0 v to 3.6v unless otherwise specified) symbol parameter min max units notes t v r v dd rise time 5 0 - ? s/v 1 t vf v dd fall time 100 - ? s/v 1 t pu power up (v dd min) to first access time 250 - ? s t pd last access to power down (v dd min) 0 - ? s notes 1 sl ope measured at any point on v dd waveform .
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 9 of 14 data retention (v dd = 2.0 v to 3.6v , +8 5 ? c ) parameter min max units notes data retention 10 - years capacitance (t a = 25 ? c , f=1 mhz, v dd = 3.3v) symbol parameter min max units notes c i/o input/output capacitance (dq) - 8 pf 1 c in input capacitance - 6 pf 1 notes 1. this parameter is char acterized and not 100% tested. ac test condit ions input pulse levels 0 to 3v input rise and fall times 3 ns input and output timing levels 1.5v output load capacitance 30 pf read cycle timing 1 (/ce low, /oe low) read cyc le timing 2 (/ce - controlled) a ( 14 : 0 ) dq ( 7 : 0 ) t rc t oh t aa t oh a ( 14 : 0 ) oe dq ( 7 : 0 ) t as t ce t ca t pc t oe t ohz t hz t ah ce
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 10 of 14 page mode read cycle timing although sequential column addressing is shown, it is not required. write cycle timing 1 (/we - controlled) note: /oe is low only to show effect of /we on dq pins write cycle timing 2 (/ce - controlled) note: see write operation section for detailed description ( page 4 ) . a ( 1 4 : 3 ) o e d q ( 7 : 0 ) t a s t c a a ( 2 : 0 ) t o e t c e t o h z t a a p t o h p t h z t p c c o l 0 d a t a 0 c o l 1 d a t a 1 c o l 2 d a t a 2 c e d i n c e a ( 1 4 : 0 ) w e t c a t p c d q ( 7 : 0 ) t w p t c w t a s d o u t d o u t t d s t d h t w x t w z t h z t w l c a ( 1 4 : 0 ) w e d q ( 7 : 0 ) t c a t p c t w s t a s t w h t d h t d s c e t a h
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 11 of 14 write cycle timing 3 (/ce low) note: /oe is low only to s how effect of /we on dq pins page mode write cycle timing although sequential column addressing is shown, it is not required. power cycle timing d i n a ( 1 4 : 0 ) w e d q ( 7 : 0 ) t w c t d h t w l a t d s t a w h d o u t d o u t t w z t w x d i n a ( 1 4 : 3 ) w e t c a t p c d q ( 7 : 0 ) t c w a ( 2 : 0 ) c o l 0 c o l 1 d a t a 0 c o l 2 t a s t d s d a t a 1 t w p t d h d a t a 2 o e t a h p t p w c t a s p t a h c e t w l c v d d t v f 1 . 0 v v d d m i n m i n v d d 1 . 0 v t v r t p u t p d a c c e s s a l l o w e d
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 12 of 14 mechanical dr awing 28 - pin soic (jedec ms - 013d variation ae) all dimensions in millimeters soic package marking scheme legend: x xx xxx= pa rt number, p= package type ( sg =soic green ) r=rev, yy=year, ww=work week, l lll l ll= lot code example: FM28V020, green/rohs soic package, rev. a, year 2010, work week 18 , lot code 9482296 ramtron FM28V020 - sg a10189482296g ramtron xxxxxxx - p r yywwlllllll pin 1 7 . 50 0 . 10 10 . 30 0 . 30 17 . 90 0 . 20 0 . 10 0 . 30 2 . 35 2 . 65 0 . 33 0 . 51 1 . 27 typ 0 . 10 0 . 25 0 . 75 45 ? 0 . 40 1 . 27 0 . 23 0 . 32 0 ? - 8 ?
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 13 of 14 32 - pin shrunk tsop - i (8.0 x 13.4 mm) all dimensions in millimeters tsop package marking scheme legend: xxxxxx= par t number, p = package/option (tg=tsop green ) r=rev code, yy=year, ww=work week, lll l lll= lot code example: FM28V020 - tg, g reen tsop package, r ev. a , year 2010, work week 18 , l ot 9482296 ramtron FM28V020 - t g a 9482296tg 1018 ramtron xxxxxxx - p r llllll l yyww p i n 1 8 . 0 0 0 . 1 0 1 . 2 0 m a x 0 . 1 7 - 0 . 2 7 t y p 0 . 5 0 t y p 0 . 1 0 m m 0 . 5 - 0 . 7 0 . 2 1 0 . 1 0 1 4 . 2 0 0 . 3 0 0 . 5 0 r e c o m m e n d e d p c b f o o t p r i n t 1 1 . 8 0 0 . 1 0 1 . 6 0 1 3 . 5 5 1 3 . 3 0 0 . 1 5 0 . 0 5 0 - 5
FM28V020 - 32kx8 f - ram rev. 2.1 june 2011 page 14 of 14 revision history revision date summary 1.0 4/15 / 20 09 initial release. 1.1 9/8 /2009 added tsop package and msl rating . expanded explanation of precharge operation. updated lead temperature rating in abs max table. 1.2 4/22 /2010 updated msl rating on soic package. 2.0 5/25 /2010 changed to pre - production status. added esd ratings. changed part marking scheme. 2.1 6/10 /2011 changed ac timing specs. changed v ol1 test condition. changed endur ance section.

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